G-Force 030 Combo with items
G-Force 030 (50Mhz PGA) , Rev 3, front
G-Force 030 (50Mhz PGA) , Rev 3, back
G-Force 030 (33Mhz PLCC) , Rev 4
G-Force 030 (upgraded to 50Mhz PGA) , Rev 4, front
G-Force 030 (upgraded to 50Mhz PGA) , Rev 4, back

Processor:

030@22MHz, EC030@25MHz, 030@33MHz, EC030@40MHz or 030@50MHz
FPU: 68882 (PGA) or surface mounted, at the same frequency as the processor.
MMU: None for EC030s, Internal in full 030s.
Max Ram: 13MB for 22/25Mhz versions, 16MB for all other versions.
Ram Type: 3 x GVP 64pin SIMM32 Slots, plus 1MB surface mounted (for 22/25MHz version), or 4MB surface mounted, for other versions.

An accelerator designed to plug into the CPU Fast slot of the A2000. The card takes GVP SIMM32 modules, which are custom 64pin 32-bit SIMM modules that are not the same as other 64-pin and 72-pin modules of the era. The card also contains a SCSI-II controller providing both an internal 50pin SCSI connector, and an external DB25 connector. A total of four board revisions cover all 'products' marketed by GVP Sales by various names.

To clean up confusion, all other related Combo/G-Force pages will eventually point here

All boards will have the Combo-030 markings on them, but they are broken down into two sub-groups:

Combo-030 Accelerators
- Surface mount 68030/68882 @ 22/33MHz with no option to change/update.
- MMU function is used to remap Kickstart to 32-bit RAM.
- Rev 3 (original) and Rev 4 (fixed a logic flaw in >16MB DPRC DMA)

G-Force 030 Accelerators
- PGA 68030 CPU and 68882 FPU, with seperate clocking options
- 25MHz & 40MHz shipped with 68EC030 CPUs, 50Mhz with full CPUs, EC chips can be replaced with full versions.
- MACH130 gate array absorbed some PCB PAL and TTL logic from the earier series.
- Support Kickstart Remap with GVPCPUCtrl or MMU (if present).
- Rev 3 (Cost-reduction/enhancement of earlier Combo-030 series), Rev 4 (FCC-related changes only)


Minimally Documented Differences

- The Rev 3 Combo-030 has a logic flaw that will cause the DPRC DMA to wrap (write) over the motherboard 16MB address space when transferring directly to >16MB 32-bit FastRAM.  The v3.14 (or higher) gvpscsi.device ROM addresses this by using the buffered DMA method through Zorro II FastRAM space (or ChipRAM) and CPU data copy (similar to a Zorro II DMA controller would need to do with >16MB addressed memory).
- The Rev 4 Combo-030 resolved the DMA logic flaw.
- The Combo-030 board have a 33C93A chip clocked at 7MHz, and are not good candidates for the GuruROM V6 in terms of SCSI speed improvements.
- The G-Force 030 boards gained GVPCPUCtrl FastROM hardware logic to make up for the non-MMU 68030 CPUs.
- All boards can benefit from the GVPCPUCtrl MoveSSP option, particularly if all onboard 32-bit RAM is mapped >16MB addressing, and if you do not make use of another tool (like in the MuLibs package) to remap certain system structures in the low memory region.
- G-Force 030 cards have their 33C93A clocked at 14MHz, so Sync SCSI via GuruROM V6 is an option.


(To be added/merged: Jumpers for the Combo-030 22/33MHz cards)

Jumpers

Common To 25, 40 and 50MHz Cards
Jumper Open Closed Default
J2 GForce030 Disabled Enabled Closed
J3 MMU Enabled MMU Disabled Open
J7 Reserved Reserved Open
J8 OmniROM (AT/SCSI) SCSI ROM Open
J9 ROM Disabled ROM Enabled Closed
J10 Reserved Reserved Open
J11 Reserved Reserved Open
J13 Reserved Reserved Open
J14 SCSI Drive Connected SCSI Drive Disconnected Either
J15 Reserved Reserved Open

 

Common To 25, 40 and 50MHz Cards
Jumper Pins 1 & 2 Pins 2 & 3 Default
CN7 Reserved Reserved 1 & 2
CN14 Reserved Reserved 2 & 3
CN15 Reserved Reserved 1 & 2
CN16 Seperate 882 Clock 68882 Uses CPU Clock 2 & 3

 

25MHz G-Force Combo Board
Jumper Pins 1 & 2 Pins 2 & 3 Default
J4 Reserved Reserved Closed
J5 Reserved Reserved Open
J6 Reserved Reserved Closed
J12 All Banks as Extended Bank 1 or 2 as Auto-Config Closed
Jumper Pins 1 & 2 Pins 2 & 3 Default
CN8 Reserved Reserved 2 & 3

 

40MHz G-Force Combo Board
Jumper Pins 1 & 2 Pins 2 & 3 Default
J4 Reserved Reserved Closed
J5 Reserved Reserved Closed
J6 Reserved Reserved Open
J12 All Banks as Extended Bank 1 or 2 as Auto-Config Closed
Jumper Pins 1 & 2 Pins 2 & 3 Default
CN8 Reserved Reserved 2 & 3

 

50MHz G-Force Combo Board
Jumper Pins 1 & 2 Pins 2 & 3 Default
J4 Reserved Reserved Closed
J5 Reserved Reserved Closed
J6 Reserved Reserved Closed
J12 All Banks as Extended Banks 1 & 2 as Auto-Config Closed
Jumper Pins 1 & 2 Pins 2 & 3 Default
CN8 Reserved Reserved 1 & 2


J8 - Selects upper or lower ROM bank image.  The earlier v3.x gvpscsi.device was paired with the (then) A3001/A3033/A3050 v3.x gvpat.device driver in the other half of the ROM image.  This was done to reduce the number of 'ROM Kits' dealers (and GVP) needed to have on a shelf, and result in a common production process.  Later ROM kits in the G-Force board era had the gvpscsi.device v4.x burned into both halves of the ROM image, so it doesn't matter.
J9 - The ROM appears in the card's I/O space when shorted.  Dissappears when open.
J14 - This jumper tells the ROM driver that there is either a SCSI device connected (activate/poll for boot), or none (just detect the board's RAM, if applicable, and set up any configuration communications ports (i.e. misc board register initialization)
CN8 and J11 dissappared from the G-Force Rev 3 to Rev 4 - purpose undocumented.
J16 appeared on the G-Force Rev 4 - purpose undocumented.

Some boards will have a 4th SIMM socket, which is directly mapped to the surface-mount memory chip space.
PAL chips differed between board revisions and clockspeeds, and part speeds do matter (affects any attemps at higher CPU clocking)
All G-Force boards have a different back-side connector gendering pattern from the earlier Combo-030 models.  This was related to the EGS 110/24 graphics board compatiblity.

The G-Force revisions are related to the A530 for the A500.

The boards have the F1 and D1 markings for components to provide SCSI bus +5 power, but they are omitted.

SCSI termination resistor packs are soldered in, making simultaneous use of the internal and external SCSI bus difficult to maintain proper termination.

Page contributors: Alex Lupták, Francisco Rabay Jr, Giaste, Robert Miranda (GVP Tech Support), Takahasi Kasiko
Updated: 5/2/2019 . Added: 12/22/2004