A full length Zorro II 33C93A-based SCSI-II controller Card + 0-8MB of Zorro II memory. 

GVP sold this product under many marketing names (HC8, HC+8, A4008, and possibly more), but they are all the same SCSI+RAM controller product.

An internal 50pin connector and an external DB25 pin connector is provided for SCSI peripherals. It has enough space to mount a hard drive on the card and has an LED header to connect to the A2000 case HD LED.  The Zorro II AutoConfign memory is added in 2MB increments up to 8MB of RAM in the form of pairs of 1MBx8 30-pin SIMMs or as two 4MBx8 30pin SIMMS. 
 

Common Memory Jumper Settings.

Using 1mb simms (in pairs)

Jumper J5 J6 J7 J8 J9
0MB OFF OFF ON OFF ON
2MB OFF ON OFF OFF ON
4MB ON OFF OFF OFF ON
6MB OFF OFF ON ON OFF
8MB OFF ON OFF ON OFF


Additional 8MB configuration setting for Rev 4, 5, I, and II, using a 2x 4MBx8 SIMM in CN10/CN11.

Jumper 8MB
J5 ON
J6 OFF
J7 OFF
J8 OFF
J9 OFF
J14 ON

 

Common Header/Jumper Functions (not all boards have every jumper)

JUMPER FUNCTION DEFAULT
J1/LED LED Connector (3-pin)  Center = (+)
J2 7/14MHz SCSI Clock  2/3=14Mhz
J3 AutoConfig Dis/Test  OFF
J4 AutoBoot ROM Enable  ON=Enabled
J5 RAM Setting  
J6 RAM Setting  
J7 RAM Setting  
J8 RAM Setting  
J9 RAM Setting  
J10 Driver Option OFF*
J11 Driver Option OFF*
J12 Driver Option OFF*
J13 Removed after Rev 2  
J14 RAM Setting  
J15 DTACK Support OFF


The boards of this controller family may have appeared under several names based upon GVP marketing.  All are identical in function, excluding some minor updates in the later revisions.  Most boards are trace-etched with GVP A2000-HC+8 Series II Rev x.  The following are the changes over the course of the product line, based upon the PCB revisions:

Rev 1 - Early revision, limited distribution.  2-layer PCB, GVP logo not on the DPRC (has a Motorola (M) symbol and part number S38GC023FD02)
Rev 2 - Full production, 4-layer PCB (and all that follow are same), same DPRC as Rev 1.  DPRC pad expanded slightly.
Rev 4 - Gains U8 (see below) and J14 (2x 4MBx8 SIMM option), loses J13 (internal use, a clock source selection).
Rev 5 - Updated DPRC package silkscreen (gains GVP logo), but no functional changes.
Rev I - PCB updated to support surface-mount components as a cost reduction in some areas, gains J15 DTACK signal pullup jumper option.
Rev II - All passives and chip logic are surface-mount.  Single pigtail power lead on most boards.  Gains silkscreen jumper settings table (may be on Rev I also).
 

PCB/Jumpers Details & Changes of Note

J3 - This undocumented jumper was for engineering test.  It forced AutoConfig to stop at the board and not configure it.
J4 - This enables or disables the boot ROM (makes it dissappear from the card address space if J4 is off).
J13 - This undocumented clock source jumper dissappeared after REV 2, as the default clock source was determined to be stable/the best.
J14 - Provided the extended memory option to use the 2x 4MBx8 SIMMs, if available.  Appeared with PCB Rev 4.
J15 - DTACK Pullup - It was discovered that some early 4.x motherboards needed some addded pullup on the DTACK signal under some expansion bus loads.  Normally not needed.
U8 - Engineering added a 74F244 to the Rev 4 PCB to buffer address lines to the SIMM memory sockets.  A full 8x load of 8-chip SIMMs could load the address lines enough off the DPRC that the memory didn't respond fast enough.  Use 80ns RAM, or (prefereably) use the 2-chip variant (1Mx4 x 2 chips) of the 1MB 30-pin SIMM, if fully loading the Rev 1 & 2 boards.
CN2 - 50-pin internal SCSI ribbon connector
CN3 - 25-pin external DB25 SCSI interface connector.

*J10/11/12 - Option jumpers for the driver to read and adjust behavior, as needed.
- On early boards, J10 may not have worked well when read by the driver, so J11 was also read.  Prior to gvpscsi.device v3.14, the 33C93A is expected to be clocked at 7MHz (J2 on 1/2), and shorting J10/J11 indicates that 14MHz clocking (J2 on 2/3) is in effect.
- On boards shipped with gvpscsi.device 3.14 and later, the 33C93A is expected to be clocked at 14MHz (J2 on 2/3), and shorting J10/J11 indicates slower 7MHz clocking.

J10/J11/J12 take on different meaning for the GuruROM V6 operations.  See the documentation provided with the GuruROM product.

Boards appear typically with a WD33C93A-04, or an AMD 33C93A (second source).  The AMD part is equal to a WD33C93A-08, but as far as the GVP FastROM 3.x/4.x or GuruROM V6, there is no functional difference.

Unfortunately, the passive SCSI terminator packs are soldered in on the Series II SCSI PCBs.  Because of this, it is best to only use an internal or an external cabling solution with the HC8 at the one 'end' of the SCSI bus cabling.  The short 2" cable for the HardCard configuration usually is okay.

The boards do not supply termination (+5) power to the cable (bus).  Parts F1 and D1 to supply and restrict electrical back feed have markins on the PCB, but the parts are omitted.

External SCSI off the DB25 needs to use proper shielded and twisted-pair (each singal with a ground) 50-wire SCSI cabling.  Use of a 25-wire parallel cable will not work.


Unique Logic Design (for a SCSI/RAM Controller)

The GVP DPRC - which stands for Dual Port RAM Controller, implements a semi-unique memory design taken from the original Amiga ChipRAM design.  The memory operates at 14MHz, just like the Amiga ChipRAM, and the CPU and the DMA controller alternate memory access on opposite clocks.  Agnus does the same thing with the CPU, although it has more important duties and can steal access cycles from the main CPU, if needed.  DPRC does not steal bus cycles from the main CPU.  The net result is that the DMA controller can transfer data at the full (7MHz equivalent) speed of a Zorro II bus on it's cycles, and the CPU can access that same memory on it's cycles, and they will never conflict.  The net result is that the OS overhead and other applications the CPU may be running can continue while I/O to/from the disk interface can occur to the onboard FastRAM - all at the same time.  For a stock 68000 7MHz system, this provides a performance gain while the Amiga is under average and high I/O conditions.  DMA transfers off the HC8 PCB operates like a standard DMA controller.

For the above reason, it is impossible to 'bus snoop' for DMA transfers (same for ChipRAM, and the shared RAM on a Bridgecard or RTG video product) with products such as AdSpeed or the Supra 28MHz 68000 accelerators.  The Amiga Zorro II bus, with many potential shared RAM regions and multiple bus masters, was not designed to support bus snooping.  Use the GVPSCSICtrl 68Cache kludge functionality to fix the design flaw in those products.  Note: These products also fail to register their non-standard cache functionality with Kickstart 2.0+ OS's Pre/PostCacheDMA() functions, a documented developer requirement, and will have probelms with the other expansion boards mentioned.

GVP's FastROM v3.x & v4.x driver, and the GuruROM V6, are fully 32-bit address-space and host environment aware.  They are highly compatible with nearly all SCSI devices with a reasonable grip on the SCSI I and SCSI II command and electrical specifications.  There is no need to modify the DMA Mask from the default 0xFFFFFFFE for high-mapped 32-bit RAM, and the MaxTransfer default of 0x7FFFFFFF.  Modifications may be necessary if a disk is to be connected to another controller.

If a DMA limiter (for off-card DMA transfers) is needed, use the v4.x driver ROM and GVPSCSCtrl options. 

The GuruROM V6 and support tools have the same functionality as the V3/V4 FastROM driver and tools set, plus it gains some additional features.

Some RAM on the card is highly suggested for A3000/A4000 use.  The gvpscsi.device v3.x/4.x will not DMA into ChipRAM due to the known bugs in some Super Buster Zorro II DMA situations with some CPU accelerator cards, and will seek out 24-bit_DMA attributed RAM, if present.  The GuruROM V6 has an override option in it's tool set to test/override the ChipRAM DMA default behavior.  The both drivers will resort to Polled I/O transfers if a suitable 24-bit DMA-capable RAM buffer is not available.

Aside from the SIMM memory slot differences, and fewer jumpers, the A500-HD8 product is functionally identical.  The Series II HC is related as far as the SCSI controller, but it has no memory options.  The A2000 RAM8/x is a Zorro II FastRAM memory-only variant.  Later GVP accelerators incorporate the SCSI-DMA functionality of this family.  Several other products use the DPRC as a Zorro II bus interface for other common PC-XT chips on the market at the time.

All v3/v4 gvpscsi.device drivers support the native TD_ 32-bit I/O functions, and the SCSI_Direct standard.  The third-party GuruROM V6 adds the TD_64 I/O functions and supports Sync SCSI communications when supported by devices.  Heed the limitations of your choice of filesystems' versions and OS version(s).  Amiga OS 3.1.4 FFS supports SCSI_Direct and will operate with larger partitions.  Earlier OS versions of FFS must heed the 2GB partition size and the 4GB media limit.  The original GVP FastPrep 2.51 and earlier will only handle the legacy 32-bit FFS partition and media limitations, so the use of newer HDToolbox is suggested for OS 3.1.4 and later.

For additional GVP V3/V4 driver information, there will be additional detail posted on the Combo/G-Force BBoAH pages.

Page contributors: Mario Misic, Robert Miranda (GVP Tech Support), Thomas Newsom
Updated: 5/2/2019 . Added: 12/22/2004